System Verilog 발표자료 : AMBA AXI BUS & Peripheral(SPI, I2C) 설계 및 UVM 검증
개발환경: Xilinx Vivado, Xilinx Vitis, Verilog, SystemVerilog, Synopsys, Verdi
BOM : Digilent Basys3 FPGA Board, Logic Analyzer
주제 : AXI BUS Protocol 활용 및 SPI, I2C 통신 Protocol 설계 및 구현
-> SPI, I2C의 Protocol의 Slave로 LED 제어 및 검증
번외,, SPI 통신 Protocol 설계 및 UVM 검증 + Verdi 활용
PPT 자료 :
코드 :
1) AXI Protocol (Master & Slave)
Code_Verilog_SystemVerilog/workspace/250512_AXI4lite_Master_Slave/250512_AXI4lite_Master_Slave.srcs/sources_1/new at main · Hee
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2) SPI Protocol (Master & Slave)
Code_Verilog_SystemVerilog/workspace/250519_SPI_Protocol/250519_SPI_Protocol.srcs/sources_1/new at main · Heeju99/Code_Verilog_
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3) I2C Protocol (Master & Slave)
Code_Verilog_SystemVerilog/workspace/250519_SPI_Protocol/250519_SPI_Protocol.srcs/sources_1/new at main · Heeju99/Code_Verilog_
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동작 영상:
1) SPI Protocol (LED 제어 동작)
2) I2C Protocol (LED 제어 동작)
발표영상 Youtube Link :